The present invention generally relates to a dynamic random access memory, and particularly to an improvement in word line control. More particularly, the present invention is concerned with an improvement in boosting the potential of word lines when reading data from a memory cell array.
A dynamic random access memory has memory cells, each of which is composed of a memory cell transistor and a capacitor, for example. Information is stored in the capacitor in the form of a charge. When reading information from a selected memory cell, a word line voltage applied to the gate of the transistor through a corresponding word line is boosted up. On the other hand, a gate insulating film of the transistor, such as a silicon oxide film is getting thinner to provide a reduced memory cell transistor. A boosted-up word line voltage applied to the gate of the memory cell transistor causes an increased intensity of the electric field between the gate electrode and diffused regions of the transistor. When the boosted-up word line voltage is being applied for a long time, a stress is continuously applied to the gate insulating film. Such a stress deteriorates the transistor, such as a decrease in the mutual conductance or a breakdown of the gate insulating film.
As is well known, the capacity of memory cell capacitors decreases with an increase in the operating speed and integration density of DRAM memory. From this viewpoint, there is a need for boosting up the potential of a selected word line to a voltage higher than at least a threshold voltage of the memory cell transistor so that the word line rise rapidly and a sufficient write voltage is applied to the gate thereof. For example, Japanese Laid-Open Patent Application No. 59-107484 discloses a semiconductor memory device in which the potential of a selected word line is boosted up to a voltage higher than the gate threshold voltage Vth of the transistor, such as a positive power source voltage Vcc, or Vcc - Vth.
As described above, the gate is maintained at a voltage higher than the gate threshold voltage Vth during readout operation. Thus, there is a problem that a large stress is applied to the gate insulating film so that the transistor is deteriorated. Further, there is a possibility that the word line voltage is decreased due to the occurrence of a leakage current at a high-potential node so that the rewriting operation or the word line reset operation cannot be performed rapidly.